PGY-I3C-EX-PD I3C Protocol Exerciser and Analyzer

PGY-I3C-EX-PD is the leading instrument that enables the design and test engineers to test the I3C designs for its specifications by configuring PGY-I3C-EX-ED as master/slave, generating I3C traffic with error injection capability and decoding I3C Protocol decode packets.

• Ability to configure it as Master or Slave
• Ability to configure BCR, LVR and DCR registers
• Supports legacy I2C slaves and Master
• Generate different I3C and I2C SDR and HDR Packets
• Flexibility to upgrade the unit TSP and TSL encoding (When it is available)
• Error Injection such CRC errors, parity errors and ACK/NACK errors
• Variable I3C data speeds
• Simultaneously generate I3C traffic and Protocol decode of the Bus
• Timing diagram of Protocol decoded bus
• Listing view of Protocol activity
• Error Analysis in Protocol Decode
• State Machine view of the I3C packets
• Ability to write exerciser script to combine multiple data frame generation at different data speeds
• USB2/3 host computer interface
• Flexibility to upgrade to the unit for evolving I3C Specification

Multidomain View provides the complete view of I3C Protocol activity in single GUI. User can easily setup the analyzer to generate I3C/I2C traffic using a GUI or script. User can set different trigger conditions from the setup menu to capture Protocol activity at specific event and decode the transition between Master and Slave. The decoded results can be viewed in timing diagram and Protocol listing window with autocorrelation. State machine view provides switching of state machine between master and slave for design validation. This comprehensive view of information makes it industry best, offering an easy to use solution to debug the I3C protocol activity.

PGY-I3C-EX-PD supports I3C traffic generation using GUI and Script. User can generate simple traffic generation using the GUI to test the DUT. Script based GUI provides flexibility to emulate the complete expected traffic in real world including error injections. In this sample script user can generate I3C traffic as below.

• SET Dynamic Address using slave static
• SETMWL with Data Parity Error
• GETMWL with Command Parity Error
• ENTHDR0 DDR mode with CRC Error

Timing view provides the plot of SCL and SDA signals with bus diagram. Overlaying of Protocol bits on the digital timing waveform will help easy debugging of Protocol decoded data. Cursor and Zoom features will make it convenient to analyze Protocol in timing diagram for any timing errors.

Protocol window provides the decoded packet information in each state and all packet details. Selected frame in Protocol listing window will be auto-correlated in timing view to view the timing information of the packet.

PGY-I3C-EX-PD supports Auto, simple and advanced trigger capabilities. Analyzer can trigger on any of the Protocol packets such as Broadcast, Directed or Private message. Advanced Trigger provides the flexibility to monitor Multiple trigger conditions and can set multiple state trigger machine. User can initiate a timer and trigger on set timer values.