PGY-I3C-EX-PD

I3C Protocol Exerciser and Analyzer

I3C Serial bus interface is emerging as a chosen interface for all future sensor connectivity in mobile phone and automotive Industry. This could also be chosen for low cost, reliable interface for future embedded electronic applications to address the new data intensive applications.

PGY-I3C-EX-PD is the leading instrument that enables the design and test engineers to test the I3C designs for its specifications by configuring PGY-I3C-EX-ED as master/slave, generating I3C traffic with error injection capability and decoding I3C Protocol decode packets.

Features
The product features are as follows:

  • Ability to configure it as Master or Slave
  • Ability to configure BCR, LVR and DCR registers
  • Supports legacy I2C slaves and Master
  • Generate different I3C and I2C SDR and HDR Packets
  • Flexibility to upgrade the unit TSP and TSL encoding (When it is available)
  • Error Injection such CRC errors, parity errors and ACK/NACK errors
  • Variable I3C data speeds
  • Simultaneously generate I3C traffic and Protocol decode of the Bus
  • Timing diagram of Protocol decoded bus
  • Listing view of Protocol activity
  • Error Analysis in Protocol Decode
  • State Machine view of the I3C packets
  • Ability to write exerciser script to combine multiple data frame generation at different data speeds
  • USB2/3 host computer interface
  • Flexibility to upgrade to the unit for evolving I3C Specification

Multi-domain View

 

Multidomain View provides the complete view of I3C Protocol activity in single GUI. User can easily setup the analyzer to generate I3C/I2C traffic using a GUI or script. User can set different trigger conditions from the setup menu to capture Protocol activity at specific event and decode the transition between Master and Slave. The decoded results can be viewed in timing diagram and Protocol listing window with autocorrelation. State machine view provides switching of state machine between master and slave for design validation. This comprehensive view of information makes it industry best, offering an easy to use solution to debug the I3C protocol activity.

Exerciser

 

PGY-I3C-EX-PD supports I3C traffic generation using GUI and Script. User can generate simple traffic generation using the GUI to test the DUT. Script based GUI provides flexibility to emulate the complete expected traffic in real world including error injections. In this sample script user can generate I3C traffic as below.

  • SET Dynamic Address using slave static
  • SETMWL with Data Parity Error
  • GETMWL with Command Parity Error
  • ENTHDR0 DDR mode with CRC Error

Timing Diagram and Protocol Listing View

 

Timing view provides the plot of SCL and SDA signals with bus diagram. Overlaying of Protocol bits on the digital timing waveform will help easy debugging of Protocol decoded data. Cursor and Zoom features will make it convenient to analyze Protocol in timing diagram for any timing errors.

 

Protocol window provides the decoded packet information in each state and all packet details. Selected frame in Protocol listing window will be auto-correlated in timing view to view the timing information of the packet.

Powerful Trigger Capabilities

 

PGY-I3C-EX-PD supports Auto, simple and advanced trigger capabilities. Analyzer can trigger on any of the Protocol packets such as Broadcast, Directed or Private message. Advanced Trigger provides the flexibility to monitor Multiple trigger conditions and can set multiple state trigger machine. User can initiate a timer and trigger on set timer values.

PGY-I3C-EX-PD Specification

 

Excerciser:
Protocol Layer 1 Master+ Four Slaves OR
5 Slaves OR
Slave with
Secondary masterI3C
I3C/I2C Traffic generation Custom I3C/I2CTraffic Generation
Simulate real world network traffic
SCL Frequency 400KHz to 13.5MHz
Voltage drive level 1 V to 3.3V at
steps of 100mV
IBI Yes, Supported
(To be tested
with other DUT)
HotJoin Yes, Supported(To be tested with other DUT)
CCC Support All CCC are supported except SETXTIME,
ENTTM, ENTAS*
SCL Duty
Cycle variation
User Define
SCL and SDA Delay User Define
Delay between two messages 400KHz to 13.5MHz
Error Injunction S0 to S5 types of errors specified
in the I3C
Specifications
CRC Errors in DDR Traffic
Preamble Errors
in DDR Traffic
ACK/NACK Errors (Slave)
Master Abort
Non-Standard Frames
Non-Standard Start, Stop and
HDR Exit Patterns
Save and load scripts
Protocol Analysis
Supports I3C and I2C Protocol Decode
Protocol views Timing Diagram view
Protocol Listing View
State machine View
Bus Diagram to
display Protocol packets
with timing
Diagram plot
Protocol Trigger Auto (Trigger on Any Packet)
Simple (Trigger
on any user defined
I3C or I2C packet)
Advanced (Multistate and Multilevel Trigger
with Timer Capability)
Capture Duration Continuous streaming Protocol data to
Host HDD/SSD
Capture Duration Protocol Error Report
S0 to S5 types of errors specified
in the I3C
Specifications CRC Errors in DDR Traffic
Preamble Errors in DDR Traffic
ACK/NACK Errors (Slave)
Master Abort
Non-Standard Frames
Non-Standard Start, Stop and HDR
Exit Patterns
Host Connectivity USB3.0/2.0 interface

Ordering Information
PGY-I3C-EX-PD I3C Protocol Exerciser and Analyzer

PGY-UFS-PA UFS Protocol Analyzer
(Shipment includes Hardware, software CD, one set probe, USB3.0 and Ethernet Cable, power adopters)
Warranty:
Hardware and software carries warranty of one year.
Probes are covered three month warranty for any manufacturing defects

Deliverables

PGY-I3C-EX-PD Unit
USB3.0 cable
PGY-I3C-EX-PD Software in CD
12V DC adopter
Flying lead probe cable with female connector to connect to DUT